| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 98 === In this thesis, we propose a high-performance dual-field elliptic curve cryptographic processor (DECP) architecture that can support all finite field operations and elliptic curve (EC) functions with arbitrary field and curve. Based on our proposed fast unified division algorithm, the operation cycles can be significantly reduced. Compared with previous works using high radix multiplication in projective coordinate, our 160-bit and 256-bit DECPs can achieve competitive performance in terms of execution cycles with only 0.29mm2 and 0.45mm2 silicon area in UMC 90nm CMOS technology by exploiting hardware sharing and ladder selection techniques. In addition, the operating frequency in prime field and binary field can be increased due to the proposed data-path separation and degree checker. To resist power analysis attack, we propose a DECP with power analysis countermeasures architecture based on the proposed unified random algorithms with only 8.4% area overhead.
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