| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 98 === Sub/Near-threshold SRAM is a significant approach to reduce power consumption in energy-constrained SoC design. Nevertheless, in sub/near- threshold region, the primary concerns of SRAM are stability and reliability instead of high-speed. In this thesis, a novel 8T sub/near-threshold SRAM is presented firstly, which has 18% improvement in write margin and 68.8% reduction in write variation (standard deviation) compared to conventional dual-port SRAM. Secondly, a 9T subthreshold SRAM is proposed to efficiently enable implementation of bit-interleaving structure. A 1kb bit- interleaved SRAM is implemented in UMC 65nm technology to verify the proposed scheme, which operates at the minimum energy point of 0.3V with 5.824pJ energy consumption per read/write operation. Thirdly, an extremely low power 0.5V 32kb 8T SRAM-based FIFO memory, which employs adaptive power control system and power gating, is implemented for healthcare applications in UMC 90nm technology, with 4.81μW power consumption. Finally, dynamic voltage scaling (DVS) reduces energy consumption by adjusting system supply voltage depending on performance requirement. A 1kb DVS 8T SRAM-based FIFO memory is implemented to operate between 0.5V (near-threshold) and 0.3V (subthreshold) in UMC 65nm technology, with 0.535μW and 0.163μW power consumption, respectively, at 625kHz reading frequency and 20kHz writing frequency. The proposed DVS FIFO memory can provide up to 69.5% power savings when low-power mode is always engaged, and there is no power overhead if the period of low-power mode is longer than 48.66μs.
|
|---|
