Through-Silicon-Via(TSV)-constrained Scan Chain Reordering for Three-dimensional(3D) Circuits
碩士 === 國立交通大學 === 電信工程研究所 === 98 === This thesis formulates the scan-chain reordering problem considering a limited number of through-silicon vias (TSVs), and further develops an efficient 2-stage algorithm. For three-dimensional optimization, a greedy algorithm named Multiple Fragment Heuristic com...
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| Format: | Others |
| Language: | en_US |
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2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/37688197039472065998 |
| Summary: | 碩士 === 國立交通大學 === 電信工程研究所 === 98 === This thesis formulates the scan-chain reordering problem considering a limited number of through-silicon vias (TSVs), and further develops an efficient 2-stage algorithm. For three-dimensional optimization, a greedy algorithm named Multiple Fragment Heuristic combined with a dynamic closest-pair data structure FastPair is proposed to derive a good initial solution at stage 1. Later, stage 2 proceeds two local refinements 3D Planarization and 3D Relaxation to reduce the wire/power cost and the number of TSVs in use, respectively. Experiments show that the proposed algorithm can result in a comparable performance to a genetic-algorithm-based method but can run at least 2-order faster, which evidently makes it more practical for TSV-constrained scan-chain reordering for 3D ICs.
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