Built-In Self-Tests for Jitter Measurement of Phase-Locked Loops

• Main Authors: Hsu, Jen-Chien, 徐仁乾
• Other Authors: Su, Chau-Chin
• Format: Others
• Language: en_US
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/30982847436181675801

博士 === 國立交通大學 === 電控工程研究所 === 98 === Signal quality of data transmission is significantly affected by clock jitter of Phase-Locked Loops (PLLs). However, production test for clock jitters is too expensive to implement. Built-In Self-Test (BIST) for clock jitter measurement becomes an alternative solution for production test. Basically, BIST methodologies are based on Time-to-Digital Converters (TDCs) which convert phase differences of a tested clock and a reference clock into low-speed digital signals for test equipments to measure. In this thesis, we proposed three kinds of TDCs and BIST circuits for different applications. The first one is designed for measuring clock jitter of charge-pump PLLs. The BIST is based on a novel high resolution TDC. Small area overhead is achieved by reusing the Voltage-Controlled Oscillator (VCO) and loop filter of the tested PLL as part of the TDC. The experiment result shows that the resolution is about one pico-second and the measurement error is smaller than 20%. The second BIST circuit is proposed for measuring timing jitter of Spread-Spectrum Clocks (SSCs). The BIST circuit can separate low-frequency phase drifting caused by frequency modulation and high-frequency jitter. Because of lack of dedicated instruments for SSC timing jitter measurement, a jitter estimation method is also developed for validating the feasibility of the BIST circuit. A 1.2GHz 10-phase Spread-Spectrum Clock Generator with a jitter measurement circuit is designed and fabricated. The experimental results show that the proposed built-in measurement approach has an error of less than 0.0026UI. The third BIST circuit is developed for testing the relative timing jitter of data and clock recovery circuits. This BIST circuit doesn’t need a high resolution delay line to achieve high accuracy measurement result, but uses calibration and curve-fitting algorithms. Calibration is done by switching the VCO of the tested PLL into free-running mode and using statistical theories to acquire accurate delay time of the delay buffers in the TDC. This BIST circuit also separates deterministic jitter and random jitter by adopting the bathtub curve-fitting algorithm and estimates total jitter at bit-error rate=10-12 level.