Built-In Self-Tests for Jitter Measurement of Phase-Locked Loops
博士 === 國立交通大學 === 電控工程研究所 === 98 === Signal quality of data transmission is significantly affected by clock jitter of Phase-Locked Loops (PLLs). However, production test for clock jitters is too expensive to implement. Built-In Self-Test (BIST) for clock jitter measurement becomes an alternative sol...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2010
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/30982847436181675801 |