| Summary: | 博士 === 國立交通大學 === 電控工程研究所 === 98 === Due to the flexibility of Petri nets (PNs) and their ability to construct various types of clear, readable and suitable plane models, PNs have been recently employed in industrial applications. In this thesis, a Logic Petri nets (LPNs) and a Boolean Petri nets (BPNs) were applied to test, diagnose, and design ladder diagrams (LDs) and to test integrated circuits (ICs).
In IC tests, the proposed LPNs model possesses the properties of a Boolean algorithm including collapsing fault and clear physical concepts because the LPNs model was constructed according to the critical truth table of combinatorial circuits. To solve generated test patterns and determine fired logical values at the site of fault in combinational circuits, the proposed approach contains a site of fault and fired logical value reasoning algorithm and a test pattern generation reasoning algorithm.
In existing LDs, the proposed BPNs was used to construct an abstract model that can directly generate test events from the transition sequence of the BPNs and can support the implementation of application-specific integrated circuits (ASIC). Moreover, in the design of programmable logic controllers (PLCs), the proposed abstract BPNs model can be constructed according to the specifications of the system or by employing the integration definition for function modeling (IDEF0). The abstract model developed in this thesis can directly generate a testing event sequence for PLC testing and diagnosing. Finally, an example of a stamping process is provided to illustrate the design, implementation, testing and troubleshooting process. Comparison of the basic elements (i.e., number of places, transitions, and arcs) of simplified Petri net controller (SPNC) (Lee, 2004) and BPNs are also given to demonstrate the usefulness of this approach.
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