Design and Realization of Embedded Compression Algorithm and VLSI Architecturefor LCD Display System

• Main Authors: Yu-Hsuan Lee, 李宇軒
• Other Authors: Tsung-Han Tsai
• Format: Others
• Language: en_US
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/71111874374273445838

博士 === 國立中央大學 === 電機工程研究所 === 98 === The modern LCD display system can be categorized into three parts: streaming part, digital TV part and LCD panel control part. All three parts exhibits two common features: computation-intensive and bandwidth-intensive. With the rapid progress of semiconductor industry, the computation-intensive issue can be properly handled by parallelism or pipeline processing. Therefore, bandwidth-intensive issue becomes more and more important in this system. The embedded compression (EC) technology is widely applied to save frame memory size and bandwidth requirement. In lossless EC scenario, the VLSI-oriented FELICS algorithm, which consists of simplified Adjusted Binary Code and Golomb-Rice Code with storage-less k parameter selection, is proposed to provide the lossless compression method for higher throughput applications. Besides, the color difference pre-processing (CDP) is also proposed to improve coding efficiency with simple arithmetic operation. Based on VLSI-oriented FELICS algorithm, the proposed hardware architecture features compactly regular data flow, and two-level parallelism with four-stage pipelining is adopted as the framework of the proposed architecture. The chip is fabricated in TSMC 0.13-um 1P8M CMOS technology with Artisan cell library. The maximum throughput can achieve 4.36 Gbit/sec. In lossless/near lossless EC scenario, the proposed high-speed EC algorithm comprises three features: (1) The associated geometric-based probability model (AGPM) is developed to construct context-modeling mechanism without context-table. (2) Develop content-adaptive Golomb-Rice code and geometric-based binary code as the entropy coding with minor order of context. (3) Provide the rate control mechanism to guarantee the saving ratio of memory bandwidth and capacity. The entire codec chip is implemented in TSMC 0.18-um 1P6M CMOS technology. The maximum throughput is as high as 6.4 Gbit/sec. Furthermore, with multi-level parallelism, the performance can be extended to QHD (2560x1440)@120Hz and QFHD@120Hz for double frame rate (DFR) technique. For video coding system, an efficient EC algorithm, including ABC-based recompression, side-clipping mechanism and average-based prediction, is proposed. With proposed EC algorithm, the compression ratio (CR) of 50% can be guaranteed with minor PSNR loss of 1.37db on average. Although EC is an additional function in video coding system, the extra encoding computation load is just 2.4% on average. Consequently, the proposed EC algorithm can be exploited to reduce the frame memory and bandwidth requirement in video coding systems.