The Design and Implementation of CRC Based Packet Error Corrector Using Parallel Architecture

• Main Authors: Ting-rong Ou, 歐亭鎔
• Other Authors: Shiann-tsong Sheu
• Format: Others
• Language: en_US
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/45809355173379866826

碩士 === 國立中央大學 === 通訊工程研究所 === 98 === Usually, data frames encapsulated in the medium access control MAC layer are protected by the well-known CRC-32 mechanism. The CRC-32 redundant information is produced by encoding the original data according to a pre-specified polynomial function. Upon the receiver receiving the data frame, it calculates the CRC-32 remainder of the received frame for determining whether the received data frame is correct or not. If the checking fails, the automatic repeat request (ARQ) protocol of MAC layer will be triggered to retransmit the erroneous data frame from transmitter to receiver. ARQ protocol is designed to achieve reliable transmissions over unreliable channel, and thus the packet loss probability is decreased. However, there is an issue that one erroneous data bit in a data frame will cause whole data frame to be retransmitted. This thesis proposes to properly store erroneous data frame(s) and combine it with the newly retransmitted frame may find out the original data frame. Based on our preliminary work [1], this thesis further utilizes the parallel architecture to construct the CRC based packet error corrector, which has the features of low circuit complexity and short processing time, as compared to the previously developed serial CRC based packet error corrector (CEC).