Low Power Charge Recycling PLA Design and Analysis

• Main Authors: Chiuan-Tai Xiao, 蕭荃泰
• Other Authors: Kai-Cheng Wei
• Format: Others
• Language: en_US
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/36549970158254811209

碩士 === 國立彰化師範大學 === 積體電路設計研究所 === 98 === The chip is advancement of manufacturing process in nowadays, it to increase design complication of digital circuit, and the transistor amount to increase in circuit, the requests of the design to power and speed are comparatively higher than before, too. The digital logic design using programmable logic array (PLA) circuit to implementation, and static PLA isn’t desirable on operation speed and chip area. This thesis using dynamic PLA circuit to design and analysis, because of dynamic PLA has high speed and predictable routing delay, and therefore it become popular in designing high performance microprocessors. In deep-submicron fabricating, the internal wire parasitic capacitance greater than transistor parasitic capacitance in the circuit, and the density increase of transistor, the wire routing length in proportion to increase, at this time, the circuit properties isn’t predictive of prior structure. Therefore, we discuss focus of analysis previous dynamic PLA structure, and presentation advantage and drawback of various structures. This thesis proposes a method of charge recycling technology of PLA which is implemented by using the parasitic capacitance of product-lines and input-lines. This scheme can reduce voltage swing on product-lines and input-lines to decrease power consumption and speed up operation. The circuit was designed by the Taiwan Semiconductor Manufacturing Company (TSMC) 0.18-μm 1P6M CMOS and 0.35-μm 2P4M CMOS technology, and analysis and compare with various dynamic PLA by simulation. Therefore, the proposed scheme can reach to low power and high speed.