| Summary: | 碩士 === 國立東華大學 === 電機工程學系 === 98 === The 10th generation of video display standard was developed in 2009 in Japan, which demands the characters of doubling frequency on 120Hz and high-resolution. It seems to be good for plasma display due to cost saving on the way toward large area of flat display, therefore shorten reset period is essential and critical for the matching the doubling display frequency and resolution on plasma display technology. We thereby propose a new reset waveform trying to shorten the reset period, and then enhance the display resolution and reduce the addressing delay by using the saved time from proposal reset waveform.
The proposed driving waveform was generated by using programmable logic gate arrays (FPGA) and DAC IC based on the address display separation technology (ADS), then amplified by a high-voltage amplifier to range of ± 200V and finally output to the panel. We detected the IR signals and discharge currents to correlate the display performance with new waveform.
In order to reduce the reset period of time, we adopt two stage of ramping slopes approach, and successfully reduce the reset period from 200us to 150us which saves 25% , and shorten the address time lag to 703ns having 22% improvement. A following benefit of the new reset waveform is addressing voltage decreasing from 65V to 45V, which meets the requirements of high operating voltage.
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