| Summary: | 碩士 === 國立東華大學 === 電機工程學系 === 98 === A low power 6-bit flash analog-to-digital converter for UWB application is presented in the thesis. High transmission data rate of wireless devices is required for ultra-wideband systems. Therefore, power consumption has a significant impact on the overall system. A low power consumption flash analog-to-digital converter is designed to adopt a new fast comparator, and to eliminate both pre-amplifier and the second level comparator. This will not only save the power consumption of the second stage pre-amplifier and the comparator, it can also reduce chip area. The presented comparator is not the traditional latch-type comparator. The amplitude of the swing is used to determine the output level of standard digital logic to be high or low.
The design of analog-to-digital converter uses Hspice and Laker software to complete the simulation and circuit layout. The process for this circuit is tsmc 0.18μm CMOS 1P6M process. The chip area is 0.478mm2 without PAD. The supply voltage is 1.8V. While input sine wave signal of 200MHz and the sampling rate of 2GS/s, ENOB is 5.03bit. SNDR and SFDR are 32.06dB and 33.99dB respectively. The overall power consumption is 80.11 mW.
Finally, a current-type 10-bit digital-to-analog converter is designed. The digital-to-analog converter uses the voltage-controled circuit to fine-tune the output of current sources, High linearity of the proposed DAC can be achieved.
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