| Summary: | 碩士 === 國立高雄第一科技大學 === 電腦與通訊工程所 === 98 === Design of 3.5 GHz Low Noise Voltage-Controlled Oscillator
Using Impedance Locus
Student： Chao-Chieh Hu Advisor： Kang-Chun Peng
Department of Computer and Communication Engineering
National Kaohsiung First University of Science & Technology
Abstract
This thesis develops a 3.5 GHz low noise voltage-controlled oscillator (VCO) by using impedance locus. In 1969, Kurokawa proposed a generalized analysis of negative-resistance oscillators that indicates the conditions necessary for stability of oscillation. The oscillator frequency and output power can be predicted by observing the device line and impedance locus. In every oscillation point, device line and impedance loci have a angle 。If the angle satisfy , then the oscillation point called stability oscillation.When ,the phase noise is lowest.Use impedance locus have better phase noise performance. In practical, the simulation and the measurement results show that VCOs which designed with impedance locus have better phase noise performance. The phase noise of the 3.5 GHz VCO has a very good phase noise as -104. dBc/Hz at 100 kHz offset frequency. That is about 6 dB better than the one without using impedance locus. The phase noise at the 3.5 GHz VCO of the PLL has a phase noise as low as -87 dBc/Hz at 10 kHz offset frequency. That is about 7 dB better than the one without using impedance locus.
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