| Summary: | 碩士 === 國立高雄第一科技大學 === 電腦與通訊工程所 === 98 === This thesis proposes a design of ZigBee transmitters using modulated frequency synthesizer for 2.45GHz . By using the fractional-N frequency synthesizer with the delta-sigma modulator (DSM) which could conquer the relevant limitations of the integral-N frequency synthesizer such as the frequency resolution , loop bandwidth and locked time . Furthermore , by using the higher order’s delta-sigma modulator to suppress the growth of fractional spurs effectively . In the physical circuit , the basic phase-locked loop consist of phase frequency detector (PFD) , voltage-controlled oscillator (VCO) , divider and loop filter (LF) . Integrating with the digital-analog converter and Xilinx Vertex-4 ML401 FPGA module by Verilog code programming to implement a modulated frequency synthesizer which with a frequency resolution of 305Hz , loop bandwidth of 200kHz and the locked time is around 13us while 87MHz step change . Besides , the measured phase noises are as good as -71dBc/Hz@100kHz and -103dBc/Hz@1MHz . The quality of modulated signals can reach a transmission rate of 2.5Mbps and the error vector magnitude (EVM) is less than 12% .
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