| Summary: | 碩士 === 國立清華大學 === 電子工程研究所 === 98 === A Frequency Synthesizer plays an important role in wireless communication systems. Both transmitter and receiver need the synthesizer to generate local oscillation frequency. The growing wireless LNA market has generated increasing interest in technologies that enable higher data rates and capacity compared to those of previous implementation. Hence, design a low power frequency synthesizer with good noise performance is a significant work.
In this work, a phase locked loops based integer-N frequency synthesizer with optimal power consumption is presented. This PLL employs an analog feedback charge pump circuit for low noise application. The oscillator is implemented by conventional LC-tank, with switch capacitance to achieve low spur and low phase noise. At 5.12GHz, the VCO system demonstrates a phase noise of -113dBc/Hz at 1MHz offset with dissipation 1.5mA at a 1.2-V supply. This corresponds to a FOM of 188dBc/Hz/mW. For the divider chain of this work, current-mode logic based frequency dividers are adopted in four-stage cascaded-dividers after LC based buffer. This will allow the system to generate a wide-locking-range characteristic. According to the post-layout simulation of the CML divider chain, they achieve a 1.2 to 7.3GHz locking range wide. This result shows that the divider chain implemented can correctly operate under possible PVT variations.
Finally, this frequency synthesizer has been fabricated in a TSMC 0.18 um 1P6M RF/Mixed-Mode Process. The whole circuits occupy an area of 1.2 x 1.3mm2.
|
|---|
