The Design and Implementation of High-speed Network Switches

• Main Authors: Hsu, Yu-Hao, 許育豪
• Other Authors: Chang, Cheng-Shang
• Format: Others
• Language: en_US
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/68081494330660488135

博士 === 國立清華大學 === 通訊工程研究所 === 98 === There is an urgent need to built high speed switches that scale with the transmission speed of fiber optics. Most switches in the current market are based on the so-called shared memory switch architecture. As the speed of fiber optics advances, the memory access speed becomes a bottleneck. A breakthrough in high-speed switch is the load balanced Birkhoff-von Neumann switch. It is proposed to resolve the memory access conflict and yield 100% throughput with high scalability. We implement the digital core of the load balanced switch in first, and then develop the analog SERDES interface to reduce the switch IC pin counts. The mixed-signal design of the switch system is then integrated successfully. In the next generation, we also implement the switch IC directly in RF domain without the use of SERDES interfaces to achieve low propagation delay and high scalability. We also propose the Combined Input and Crosspoint Queueing (CICQ) switch with the dynamic frame sizing algorithm for the possibility of O(logN) delay. It is formally shown that such the CICQ switch indeed achieves 100% throughput for certain Poisson-like traffic models. Moreover, such a CICQ switch only requires a two-cell buffer at each crosspoint when there is only unicast traffic. Unlike input-buffered switches, the dynamic frame sizing algorithm also achieves 100% throughput in the setting of multicast traffic. This is done at the cost of increasing the buffer size at each crosspoint.