| Summary: | 碩士 === 國立臺北大學 === 電機工程研究所 === 98 === This paper presents a Class D Power Audio Amplifier, using ternary Pulse-Width-Modulation (PWM) method to eliminate output filter. Full Bridge configuration acts as an output stage that operates with 1.5 supply voltage. Its upper and lower Half Bridge output signal is differential to each other to decrease the noise interference. In addition, it eliminates the need for external coupling capacitors on the output, reducing off chip elements requirement. we use negative feedback formed by resistor and capacitor to reduce the total harmonic distortion and increase the stability of entire Class D Power Audio Amplifier. Clock generator integrated with spread spectrum circuit is used to decrease the effect of Electromagnetic Interference. Spread Spectrum circuit can be disabled to identify its advantages and disadvantages to Class D Power Audio Amplifier system. We use H-spice simulation software to verify the circuit behavior and implemented the integrated circuit design in TSMC 2P4M35 CMOS process. In the pre-simulation results：The efficiency can achieve 92%, and total harmonic distortion (THD) around 0.05% with 8 Ω load at 10 KHz sine wave. In the Chip measure, ternary PWM signal from the upper output stage and lower output stage can be obtained, as described in this thesis.
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