Design Space Exploration of Demand-based FTL Design for Server SSDs

• Main Authors: Han-Lin Li, 李翰林
• Other Authors: 楊佳玲
• Format: Others
• Language: en_US
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/94787049583384496921

碩士 === 臺灣大學 === 資訊工程學研究所 === 98 === Flash memory has become a popular storage alternative for many devices with the continuing improvements on its capacity, reliability, higher performance, and much lower power consumption than mechanical hard drives. But special characters of flash memory lead the need to design a low cost Flash Translation Layer(FTL) to translate logical address to physical address. In this paper, we proposed a novel FTL scheme named Spatial-locality Aware FTL(SAFTL), which can exploit spatial locality for FTL to save SRAM size. Instead of putting whole mapping table in SRAM, SAFTL stores mapping table in flash and uses a cache with multiple cache line sizes to cache mapping entries which may be used in the future. SAFTL adjusts the cache line size to make sure all data which will be used in the near future will be cached. We analyzed the impact of cache line size to hit rate and performance. An interesting finding is high hit rate doesn’t lead to high performance. Our evaluation results show that SAFTL can achieve same performance as previous works with only 9.1% SRAM size.