Routing Algorithms for Flip-Chip Designs

• Main Authors: Po-Wei Lee, 李柏緯
• Other Authors: Yao-Wen Chang
• Format: Others
• Language: en_US
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/58883910265994656961

碩士 === 臺灣大學 === 電子工程學研究所 === 98 === The flip-chip package is introduced for modern IC designs with higher integration density and larger I/O counts. As the advance of technology, the flip-chip routing problems become more and more important. The problems can be classified into two categories: (1) the free-assignment routing problem and (2) the pre-assignment routing problem. Both routing problems occur in real applications and thus have received dramatically increasing attention recently. This thesis studies both routing problems with two research topics. On the other hand, modern flip-chip designs might incur a significant number of obstacles in the routing regions due to pre-placed modules and/or pre-routed nets, which is also concerned in this thesis. In the first topic, we consider the obstacle-avoiding free-assignment flip-chip routing problem. The free-assignment problem has been shown to be solved well by using network-flow formulation. To our best knowledge, however, existing published works do not consider obstacles, which might not apply to designs with obstacles well. To remedy the insufficiency, this thesis presents the first work to solve the free-assignment flip-chip routing problem considering obstacles. We first propose a new effective network-flow model to remedy the insufficiency of the previous models in obstacle handling. Based on the new model, a two-stage technique of global routing followed by detailed routing is introduced for flip-chip routing. The global routing converts the routing problem into the minimum-cost flow problem to compute a routing topology. The detailed routing then determines the final layout based on the routing topology. Compared with a state-of-the-art work with reasonable extensions to handle obstacles, the experimental results show that our algorithm is effective (100% routability for all circuits) and efficient. In the second topic, we consider the pre-assignment flip-chip routing problem first, and then extend the proposed algorithm to consider obstacles. That we advance gradually is due to the difficulty of the pre-assignment routing problem, which limits the quality of previous work. Based on the concept of routing sequence exchange, we propose a very efficient global routing algorithm by computing the weighted longest common subsequence (WLCS) and the maximum planar subset of chords (MPSC) for pre-assignment flip-chips. We observe that the existing work over constrains the capacity of a routing tile, which might miss some critical solution space with a better routing solution (e.g., smaller wirelength), and provide a remedy for this insufficiency to identify a better solution in a more complete solution space. We also develop a constant-time routability analyzer to check if a given set of wires can pass through a tile. Experimental results show that our router can achieve a 122X speedup with even better solution quality (same routability with slightly smaller wirelength), compared with a state-of-the-art flip-chip router based on integer linear programming (ILP).