| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 98 === Along with the increasing complex and computation power of modern embedded systems, an embedded operating system is necessary to make full use of such systems. To lower down the cost and power dissipation, the use of SDRAM devices becomes indispensable in such systems. However, the interface between the processor and the SDRAM devices is not an easy task. It needs to be designed with care.
In this thesis, we propose an AMBA compatible SDRAM controller. It is composed of an AHB user access interface, a controller core, and a PHY. The most important features of this controller are as follows. First, it is a parameterized module so that it can be easily adapted to work with different memory devices. Second, it provides a portable user access interface with that it can be easily integrated with any bus system. Third, a dual-clock-domain design allows both the user access interface and the memory controller to work in different clock domains. Fourth, the use of a configuration register file allows the delay timing and the mode register setting of SDRAM devices, and the operation setting of controller as well to be configurable. Fifth, many special designs, including a power saving controller, a dynamic access policy selector, an individual bank delay time count, and a separated commend/data burst controller, are used to reach high performance and to lower the power dissipation.
The designed controller has been integrated with the Proto-3 ARM9TM core, designed previously in the lab, and AMBA2.0 system. The integrated system has been successfully implemented with the Xilinx Spartan-3 XC3S1500-4FG676 FPGA, and can reliably access the Micron MT46V16M16FG-75 DDR SDRAM. The proposed dynamic memory controller consumes 2502 LUTs. The maximum frequency of AHB access interface is 79 MHz and of memory controller is 110 MHz.
|
|---|
