| Summary: | 碩士 === 國立高雄大學 === 電機工程學系碩士班 === 98 === In recent years, silicon-on-insulator (SOI) four-gate transistors have already caused extensive attention. With improved current drive and short-channel characteristics, semiconductors depicts not only switch from bulk to SOI, but also evolve from single-gate planar SOI transistors to multiple-gate devices. Among those novel SOI devices, double- and triple-gate transistors have been demonstrated and modeled. However; the SOI four-gate transistor with low-power and low-noise operation, high intrinsic DC gain, radiation hardness that becomes a promising candidate has not been analytically modeled yet.
In this thesis, based on the exact solution of the Poisson equation, we successfully develop an analytical short-channel behavior model for SOI four-gate transistor. Without any fitting parameters, these analytical results are useful in predictive compact modeling of SOI four-gate transistor. The model explicitly shows the distribution of electric potential, short channel threshold voltage roll-off, and drain-induced-barrier-lowing (DIBL) effect. The model is verified by published numerical simulations with close agreement. This model not only gives physical insights into the device physics but also offers the basic designing guidance of the SOI four-gate transistor. Due to its computational efficiency, this model can be applied for SPICE simulation.
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