Design of Tunable Ring Oscillator and Output Buffer

• Main Authors: Shih-Wei Tseng, 曾世緯
• Other Authors: 劉偉行
• Format: Others
• Language: zh-TW
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/hw2zje

碩士 === 國立虎尾科技大學 === 光電與材料科技研究所 === 98 === A ring oscillator, which uses digital codes to control the transmission paths, has been proposed in this thesis. As the transmission paths changes, different output frequencies are generated. Moreover, a current-adjusted inverter is used as the last output stage. Therefore the output frequency can be further calibrated. Comparing to the conventional oscillators, the proposed one can have multiple output frequencies. The proposed digital-code-controlled ring oscillator has been simulated with HSpice where 0.35μm mixed-signal 2P4M polycide 3.3/5V fabricated parameters have been adopted. Simulation results show that, 32 different output frequencies can be obtained. The maximum frequency is 1.05GHz and the minimum frequency is 188.4MHz. As the supply voltage is 3.3 V and the load capacitance is 20 pF, the maximum power consumption is 402.52 mW. Since the oscillator can generate different output frequencies, the low output frequency needs less number of stages of cascaded buffers while the high output frequency needs more. If both the low output frequency and the high output frequency use same stages of cascaded buffers, it will bring extra power consumptions at low output frequency. In this thesis, an adaptive stage cascaded buffer has been proposed. In order to reduce additional power dissipation, the stages of cascaded buffers will be adjusted according to the output frequency. In the proposed circuit, as the input signal frequency varies from 1MHz to 100MHz, the corresponding stage of output buffer can be increased from 1 to 3. The proposed adaptive cascaded buffer has been simulated with HSpice where 0.35μm mixed-signal 2P4M polycide 3.3/5V fabricated parameters have been adopted. As the supply voltage is 3.3V, load capacitance is 15pF, and the input signal frequency is from 1MHz to 100MHz. The post-layout simulation results show that, the power consumption of the proposed circuit can reduce 110.22mW and 105.93mW, respectively, as compared to the conventional buffer.