DESIGN AND IMPLEMENTATION OF PIPELINEDAES-OCB ALGORITHM
碩士 === 大同大學 === 電機工程學系(所) === 98 === In this thesis, we introduce the Rijndael mathematical preliminaries. We also introduce the AES and OCB mode algorithm. In the thesis, which designed a high speed, 5-stage pipelined AES-OCB cipher. All of the modules in this chip are described by using Verilog la...
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| Format: | Others |
| Language: | en_US |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/95001270942634595135 |
| Summary: | 碩士 === 大同大學 === 電機工程學系(所) === 98 === In this thesis, we introduce the Rijndael mathematical preliminaries. We also introduce the AES and OCB mode algorithm. In the thesis, which designed a high speed, 5-stage pipelined AES-OCB cipher. All of the modules in this chip are described by using Verilog language and used ModelSim to simulate it. The operation data path operates at 100 MHz resulting in a data throughput of 1066.67 Mbits/sec.
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