An FPGA Profiling Assistant to Reduce Probe Effects

• Main Authors: Keng-Hau Yang, 楊耿豪
• Other Authors: Tien-Fu Chen
• Format: Others
• Language: en_US
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/86477972926340226207

碩士 === 國立中正大學 === 資訊工程研究所 === 99 === With the variety of embedded systems developing rapidly, the importance of profiling tools is highlighted, as demand for system and application performance increases every year. The purpose of profiling tools is intended to determine which part of design could be improved or optimized, and thus to improve the overall performance. There are some important indicators to estimate the effect of profiling tool, such as low overhead (accuracy), fast convergence, flexibility, portability, low storage impact. According to different profiling methods would cause different characteristics. In these indicators, the most important indicator which is highly paid close attention to is low overhead for profiling designers. This indicator impacts the result of profiling tool. No matter how flexible (portable, fast convergence, etc.) the tool is, the low accuracy will reduce the motivation of users to use this tool. So, most profiling designers tend to improve their tools to low overhead. In this paper, we propose a FPGA supported methodology to assist the profiling tool to reduce profiling overhead by divide some extra jobs which are added by profiling tool to decrease the workload of processor. Therefore the accuracy and low storage impact will be improved.