| Summary: | 碩士 === 長庚大學 === 電機工程學系 === 99 === The parity check matrixs of low-density parity-check (LDPC) codes and majority-logical decodable (MLD) codes both have the orthogonal property. It can be observed for each column, there exists a set of rows orthogonal on the column in the parity check matrixs of low-density parity-check (LDPC) codes. However, for one-step majority-logic decodable (OSMLD) codes , the rows of he parity check matrixs only are orthogonal on the last bit position. So, the decoding algorithm of LDPC codes needs to be modified for decoding OSMLD codes.
The min-sum algorithm of LDPC codes is simple and easy to be implemented. Therefore, we modify the min-sum algorithm to decode OSMLD codes.
The simulation results show that this modified decoding algorithm compared with the traditional weighted majority-logic decoding, achieves better bit-error-rate performance. In addition, MLD codes is belongs to cyclic codes. We employ the cyclic structure to design an efficient hardware implementation of the new technique.
Keywords: min-sum algorithm, LDPC codes, MLD codes, majority logic decoding weights
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