| Summary: | 碩士 === 中華大學 === 電機工程學系(所) === 99 === In many circuits, PLL “Phase Locked Loops” plays an important role in a high speed output clock to follow the slow input clock. Examples of application that uses PLL include clock and data recovery, delay locked loops, clock synthesis, and synchronization. In this thesis, our PLL is locked at 2.4GHz. By combining a VCO,which is a ring oscillator composed of 3-stage delay cell、a TSPC typePFD、a divided-by-16 frequency divider and a DC-balanced output, we obtain a low jitter performance.
The PLL have been designed and fabricated in a 0.35um TSMC CMOS Mixed Signal technology .The chip area is567 μm *672 μm. The VCO output frequency is 2400MHz. The supply voltage is 3V. The performance of peak to peak jitter is 2ps at 2.4GHz.
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