A 2.4GHz PLL designed by 0.35um CMOS Process

碩士 === 中華大學 === 電機工程學系(所) === 99 === In many circuits, PLL “Phase Locked Loops” plays an important role in a high speed output clock to follow the slow input clock. Examples of application that uses PLL include clock and data recovery, delay locked loops, clock synthesis, and synchronization. In thi...

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Main Authors:	Hui-Ling Chen, 陳慧菱
Other Authors:	Tien-Min Chuang
Format:	Others
Language:	zh-TW
Published:	2011
Online Access:	http://ndltd.ncl.edu.tw/handle/50205773325885175146

id	ndltd-TW-099CHPI5442008
record_format	oai_dc
spelling	ndltd-TW-099CHPI54420082015-10-13T20:22:58Z http://ndltd.ncl.edu.tw/handle/50205773325885175146 A 2.4GHz PLL designed by 0.35um CMOS Process 一個使用0.35um CMOS製程設計的 2.4GHz鎖相迴路 Hui-Ling Chen 陳慧菱碩士中華大學電機工程學系(所) 99 In many circuits, PLL “Phase Locked Loops” plays an important role in a high speed output clock to follow the slow input clock. Examples of application that uses PLL include clock and data recovery, delay locked loops, clock synthesis, and synchronization. In this thesis, our PLL is locked at 2.4GHz. By combining a VCO,which is a ring oscillator composed of 3-stage delay cell、a TSPC typePFD、a divided-by-16 frequency divider and a DC-balanced output, we obtain a low jitter performance. The PLL have been designed and fabricated in a 0.35um TSMC CMOS Mixed Signal technology .The chip area is567 μm *672 μm. The VCO output frequency is 2400MHz. The supply voltage is 3V. The performance of peak to peak jitter is 2ps at 2.4GHz. Tien-Min Chuang 莊添民 2011 學位論文 ; thesis 0 zh-TW
collection	NDLTD
language	zh-TW
format	Others
sources	NDLTD
description	碩士 === 中華大學 === 電機工程學系(所) === 99 === In many circuits, PLL “Phase Locked Loops” plays an important role in a high speed output clock to follow the slow input clock. Examples of application that uses PLL include clock and data recovery, delay locked loops, clock synthesis, and synchronization. In this thesis, our PLL is locked at 2.4GHz. By combining a VCO,which is a ring oscillator composed of 3-stage delay cell、a TSPC typePFD、a divided-by-16 frequency divider and a DC-balanced output, we obtain a low jitter performance. The PLL have been designed and fabricated in a 0.35um TSMC CMOS Mixed Signal technology .The chip area is567 μm *672 μm. The VCO output frequency is 2400MHz. The supply voltage is 3V. The performance of peak to peak jitter is 2ps at 2.4GHz.
author2	Tien-Min Chuang
author_facet	Tien-Min Chuang Hui-Ling Chen 陳慧菱
author	Hui-Ling Chen 陳慧菱
spellingShingle	Hui-Ling Chen 陳慧菱 A 2.4GHz PLL designed by 0.35um CMOS Process
author_sort	Hui-Ling Chen
title	A 2.4GHz PLL designed by 0.35um CMOS Process
title_short	A 2.4GHz PLL designed by 0.35um CMOS Process
title_full	A 2.4GHz PLL designed by 0.35um CMOS Process
title_fullStr	A 2.4GHz PLL designed by 0.35um CMOS Process
title_full_unstemmed	A 2.4GHz PLL designed by 0.35um CMOS Process
title_sort	2.4ghz pll designed by 0.35um cmos process
publishDate	2011
url	http://ndltd.ncl.edu.tw/handle/50205773325885175146
work_keys_str_mv	AT huilingchen a24ghzplldesignedby035umcmosprocess AT chénhuìlíng a24ghzplldesignedby035umcmosprocess AT huilingchen yīgèshǐyòng035umcmoszhìchéngshèjìde24ghzsuǒxiānghuílù AT chénhuìlíng yīgèshǐyòng035umcmoszhìchéngshèjìde24ghzsuǒxiānghuílù AT huilingchen 24ghzplldesignedby035umcmosprocess AT chénhuìlíng 24ghzplldesignedby035umcmosprocess
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A 2.4GHz PLL designed by 0.35um CMOS Process

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