A 2.4GHz PLL designed by 0.35um CMOS Process
碩士 === 中華大學 === 電機工程學系(所) === 99 === In many circuits, PLL “Phase Locked Loops” plays an important role in a high speed output clock to follow the slow input clock. Examples of application that uses PLL include clock and data recovery, delay locked loops, clock synthesis, and synchronization. In thi...
Main Authors: | , |
---|---|
Other Authors: | |
Format: | Others |
Language: | zh-TW |
Published: |
2011
|
Online Access: | http://ndltd.ncl.edu.tw/handle/50205773325885175146 |