| Summary: | 碩士 === 逢甲大學 === 通訊工程所 === 99 === In this thesis, the low noise amplifier (LNA) for K band application. The circuits used in this study were realized by Taiwan Semiconductor Manufacturing Company(TSMC) 0.18 μm CMOS process of provided by the National Chip Implementation Center(CIC). The advantages of the process include high yield, low cost and high integration for RF circuit design.
A simple circuit structure is used to design the good-performance 24 GHz low noise amplifier. First, I will use cascade circuit and than TSMC''s inductor module design and will be replaced by self-inductance, in addition to improving the chip design area, and measurement results: chip size is 0.36 mm2, gain is 5.62 dB, noise figure is 5.68 dB, and power consumption is 19.16 mW. And second the cascode technique is used to reduce the low power consumption, and measurement results: chip size is 0.34 mm2, gain is 4.07 dB, noise figure is 7.2 dB, and power consumption is 6.3 mW. Finally the chip used transformer and current-reused, achieve high gain and low noise: chip size is 0.54 mm2, gain is 19.23 dB, noise figure is 4.71 dB, and power consumption is 18.63 mW.
|
|---|
