| Summary: | 碩士 === 崑山科技大學 === 電子工程研究所 === 99 === In this paper, the study is divided into four parts. The first part (NPSS) on the production aspect ratio ranges from 2.00 to 2.50 nano-imprint technology; the second part of the fourth part is to use Pitch: 6 μm ~ 800 nm Diameter: 3 μm ~ 400 nm and depth changes and to smooth the voltage measurement method to measure junction temperature.
Part I: study design to prove the structure of the sapphire substrate (NPSS) and traditional (CSS) of the junction temperature measurement (Junction Temperature) and the light output of the comparison in (NPSS) changes in production methods of the aspect ratio range of 2.00 nm to 2.50 nm nano-imprint lithography. Junction temperature measurement method for the forward voltage measurement method, measurement nano-imprint structure superior to the traditional structure of temperature and thermal resistance has dropped significantly, nano-imprint of the light output power from 11% to 27% .
Part II to Part IV: use different spacing of nano-structural changes in 6 μm ~ 800 nm diameter of 3 μm ~ 400 nm depth of 1.2 μm, 800 nm, 400 nm of (NPSS) and traditional (CSS) of junction temperature measurement (Junction Temperature) and comparison of light output, and measure alternating current (mW), (IV) characteristics, (Life Curve Function) and variable temperature measurements. Junction temperature measurements that, in the nano-structure changes in the spacing and diameter are closely Kansai, nanostructures Chip operating current of 20 mA in the next 3 μm ~ 400 nm portion of substation spacing and diameter as lower optical power scaling.
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