Investigation of Interdigitated Back Contact Structure for Monocrystalline Silicon Solar Cells

碩士 === 國立中興大學 === 材料工程學系所 === 99 === Recently, the interdigitated back contact solar cell (IBC-SC) has received much attention because the metal electrodes can be fabricated on the rear side of the cell. The IBC-SC has no shadowing effect. In this thesis, firstly, the process recipes including surfa...

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Bibliographic Details
Main Authors: Chih-Kuang Yao, 姚祉光
Other Authors: Dong-Sing Wuu
Format: Others
Language:zh-TW
Published: 2011
Online Access:http://ndltd.ncl.edu.tw/handle/90811707706579088876
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Summary:碩士 === 國立中興大學 === 材料工程學系所 === 99 === Recently, the interdigitated back contact solar cell (IBC-SC) has received much attention because the metal electrodes can be fabricated on the rear side of the cell. The IBC-SC has no shadowing effect. In this thesis, firstly, the process recipes including surface texturization, anti-reflection coating, and diffusion process were established. Then, the design and study of standard processes for the silicon wafer verification were performed. The IBC-SC was fabricated using high-temperature diffusion and photolithography techniques. The pattern design of interdigitated metal electrodes, phosphorus diffusion, SiNx passivation on cell edge, the depth of boron diffusion, the effect of back surface field (BSF) around, and phosphorus concentration of front surface field (FSF) were studied. Finally, the effects of silicon wafer thickness, resistivity, and lifetime on the IBC-SC performance were investigated. The experimental results showed that the IBC-SC with BSF and FSF had more obvious diode characteristics. The SiNx passivation on cell edge had more obvious diode characteristics. Moreover, the emitter diffusion depth should be shallower. The pattern of BSF around could improve the shunt resistance (0.31 to 1.8 Mohm). Furthermore, a smaller FSF concentration was favorable. The conversion efficiency of 11.85 % on the rear side and 6.78 % on the front side for the IBC-SC fabricated using standard processes could be obtained. For the wafer verification, it was found that the thinner wafer (675 to 300 um) could lead to higher cell efficiency (3.06 to 7.26 %). The smaller the wafer resistivity (6.37 to 4.92 ohm•cm), the higher the cell efficiency (0.95 to 9.41 %). The longer wafer lifetime (35 to 169 us) would also lead to higher cell efficiency (3.78 to 8.52 %).