| Summary: | 碩士 === 國立中興大學 === 資訊科學與工程學系所 === 99 === Buffer cache replacement algorithm is an important part of the operation system. A well-behaved replacement algorithm must efficient utilize the buffer cache space to reduce the number of disk accesses so as to increase the system performance. Traditional buffer cache replacement, like LRU scheme, cannot handle sequential and loop access pattern, and thus many researchers have been proposed new buffer cache replacement schemes to solve the problem by properly handling these access patterns. One of the well-known solutions is the LIRS buffer cache replacement. However, when many applications execute concurrently, LIRS cannot manage the buffer cache properly and would replace the wrong blocks. In this thesis, we exploit the program counter information to enhance LIRS buffer cache replacement. The experimental results show that our new management mechanism can effectively enhance the LIRS buffer cache replacement scheme and improve the hit ratios.
|
|---|
