| Summary: | 碩士 === 國立中興大學 === 電機工程學系所 === 99 === The large data bandwidth demand due to the ever increasing video resolution has posed a big challenge on the wireless multimedia network. How to alleviate the communication bandwidth without suffering from any content loss is the key point to tackle such a challenge. Targeting on the application of wireless video playback projection, this thesis investigates on embedded lossless video compression schemes and presents a HW/SW codesign based implementation. The scheme is effective in compression efficiency and requires low computing complexity. The proposed scheme adopts a single-banded texture predictor and a color-correlation based transformation to enhance the efficiency. With the employment of techniques such as frame classification, prediction error feedback mechanism, smooth binary mode detector, and adaptive Golomb Codec, the proposed scheme can outperform the FELICS[1] scheme by 49% in terms of compression ratio. The performance edges against The JPEG-LS[2] and JPEG-LS are 4.6% and 72.4%, respectively.
In the second part of the thesis, a Mixed Rate Control System using an adaptive algorithm is proposed. By examining the coding property of Golomb codec and making use of 3 different coding lengths in binary mode, compression ratio can be adjusted to meet the bandwidth constraint with controlled PSNR loss. The experimental results show that our rate control scheme is capable of reducing the bit rate by 13.2% while maintaining a near lossless video quality with PSNR values greater than 50dB.
Our embedded Compression system is developed on a platform containing an ARM926-EJS processor and a Xilinx Spartan-3 FPGA. The design is partitioned into software and hardware sections. The software section implements the functions of coefficient control and frame information display. The hardware section realizes the computing kernel to achieve the speed up. Taking data dependence into account, the hardware design employs various techniques such as pipelining, parallel processing, and data sharing to improve the performance. Additional firmware design is also developed, which interfaces with the "Master Wrapper" to facilitate a high throughput data movement between the hardware and software sections. Based on CIC''s MorPack platform, our system can perform embedded video compression at a speed of 11.43 fps for 800X480 RBG images. Besides the FPGA prototyping, the hardware section design is also converted to a chip implementation. The chip design has a gate count of 153.5M and can operate at 200 MHz. The equivalent frame rate is 67.42 fps for 1920X1080 sized images.
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