A High-Speed Low-Voltage Differential-Signal Interface Design
碩士 === 國立暨南國際大學 === 電機工程學系 === 99 === This thesis presents a design of high-speed transmitter and receiver for low-voltage different signaling transmission interface. For achieving high-speed operation, an AC-coupled positive feedback path is added into the transmitter circuit for providing high-spe...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/62254883491768557458 |
| Summary: | 碩士 === 國立暨南國際大學 === 電機工程學系 === 99 === This thesis presents a design of high-speed transmitter and receiver for low-voltage different signaling transmission interface. For achieving high-speed operation, an AC-coupled positive feedback path is added into the transmitter circuit for providing high-speed conversion. In addition a current-control circuit is employed to reduce the power dissipation. The receiver uses a complementary differential pair to get a wide range of common voltage. Furthermore, a folded-cascode type comparator is used for high speed operation.
A chip including the circuits of transmitter and receiver was implemented and verified by using TSMC 0.18-μm CMOS technology. The core area of the transmitter and receiver is 275μm × 140μm and 102μm × 96μm, respectively. The transmitter and receiver can operate at 2G/bs. The power consumption of the transmitter and receiver is 27mW and 31mW, respectively.
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