| Summary: | 碩士 === 國立交通大學 === 電機學院碩士在職專班電子與光電組 === 99 === As the increasing demands for low-power and high data-rate wireless communication, conventional wireless local area network of IEEE 802.11 a/b/g has found it difficult to suffice these requirements. In this thesis, the design methodology and implementation of a 3.1~10.6 GHz direct-conversion transmitter for UWB application are presented according to the recently published IEEE 802.15.3a specification. The CMOS integrated 3-GHz to 10.6-GHz transmitter for full-band UWB applications is proposed and designed in 0.13-μm CMOS technology. The designed UWB transmitter is integrated with a quadrature up-conversion mixer and a balanced RF amplifier; for measurement purpose of quadrature LO/ IF signals generation, a divide-by-2 frequency divider and a 3-stage cascaded poly-phase filter are also designed in this chip. The technique of inductance peaking has been adopted to achieve full band operation for UWB applications.
Based on the measurement results, the transmitter has an average conversion gain of 10.25 dB with the gain ripple of around ±2.9 dB among frequency 3.1 ~ 6.2 GHz. The average output 1-dB compression point (OP1dB) of the measured bands is 5.57 dBm and the average OIP3 of the measured bands is 17.38 dBm. The transmitter dissipates the power of 49 mW from the supply voltage of 1.2 V and occupies the chip area of 1930×1635 μm2. The divide-by-2 divider of measurement purpose consumes 49.3 mW at most, which is much larger than the simulation result.
A discussion about the malfunction of the transmitter and the extraordinary high power consumption of the frequency divider is made; furthermore, a modification and revised post-simulation of the transmitter are proposed and done for further verification. In the revised post-simulation results, the proposed transmitter is confirmed to be suitable for low-power and high data-rate wireless communication systems. Future research will be conducted to implement a thorough transceiver for UWB applications.
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