| Summary: | 碩士 === 國立交通大學 === 資訊科學與工程研究所 === 99 === This thesis presents an energy-efficient fast independent component analysis (FastICA) processor with high-dimensional preprocessing unit for eight-channel electroencephalogram (EEG) signal separation. The main contributions are as follows. 1) Energy-efficient FastICA using early determination scheme, 2) high-dimensional and low-area eigenvalue decomposition (EVD) using CORDIC reuse scheme for the preprocessing unit; 3) low computation time using four parallel one-unit architecture; 4) high-accuracy piecewise linear approximation for the hyperbolic tangent in one-unit operation; 5) low-area one-unit architecture using hardware reuse scheme. The resulting power dissipation of the FastICA computations for eight-channel EEG signal separation is 16.35mW@100MHz at 1.0V. Compared with the design without early determination, the proposed FastICA processor implemented in UMC 90nm 1P9M CMOS process with a core area of 1.221x1.218 mm2 can achieve energy reduction by 41.38%. From the post-layout simulation results, the absolute correlation coefficients for mixed signals and EEG signals are at least 0.98 and 0.83, respectively.
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