A Low-Power Low-Voltage Dual-Path Pipelined ADC
碩士 === 國立交通大學 === 電子研究所 === 99 === With recent application on higher speed and higher integration capability of circuits; The trend that the channel length of MOS transistor is smaller and the thinkness of gate oxide also becomes thinner. Therefore, the intrinsic gain of MOS transistor is lower and...
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ndltd-TW-099NCTU54280202016-04-18T04:21:37Z http://ndltd.ncl.edu.tw/handle/41878529653789855808 A Low-Power Low-Voltage Dual-Path Pipelined ADC 低功率低電壓雙路管線式類比數位轉換器 Chai, Angelia Yolanda 翟芸 碩士 國立交通大學 電子研究所 99 With recent application on higher speed and higher integration capability of circuits; The trend that the channel length of MOS transistor is smaller and the thinkness of gate oxide also becomes thinner. Therefore, the intrinsic gain of MOS transistor is lower and the operation voltage is also reduced. By the demand of integrate analog-to-digital converter with digital signal-processing system in the same chip (SOC), a low-power low-voltage analog-to-digital converter is an important key factor in mixed signal system nowadays. The improved Pipelined analog-to-digital converter adopts a Dual-Path structure. It utilizes two seperated analog-to-digital converter pathes with inaccurate specifications to generate a high accurate signal value. By a large reducing of the accuracy required in this novel strcture will achieve a low-power and low-voltage implement what we explore. Furthermore, a novel OpAmp circuit is also addressed in this thesis. By utilizing the methods of feedforward and current-ratio, it realizes an OpAmp of high DC gain without capacitor compensation. Then, we utilize this novel OpAmp in the Dual-Path Pipelined analog-todigital converter what we mentioned above. To make matters even more exciting, by the particular structure of Dual-Path Pipelined analog-to-digital converter, we can design this OpAmp under unusual specifications to attain to an attractive lower power value. This complete circuit is designed with a 90nm CMOS technology. Power supply voltage is 1 V, input signal amplitude is 1.4 Vpp, resolution is 11-bit, the maximum sampling frequency is 200MHz. At Nyquist rate, the maximum power consumption is 5.3mW. Wu, Jieh-Tsorng 吳介琮 2010 學位論文 ; thesis 107 zh-TW |
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碩士 === 國立交通大學 === 電子研究所 === 99 === With recent application on higher speed and higher integration capability of circuits;
The trend that the channel length of MOS transistor is smaller and the thinkness of gate oxide
also becomes thinner. Therefore, the intrinsic gain of MOS transistor is lower and the
operation voltage is also reduced. By the demand of integrate analog-to-digital converter
with digital signal-processing system in the same chip (SOC), a low-power low-voltage
analog-to-digital converter is an important key factor in mixed signal system nowadays.
The improved Pipelined analog-to-digital converter adopts a Dual-Path structure. It
utilizes two seperated analog-to-digital converter pathes with inaccurate specifications to
generate a high accurate signal value. By a large reducing of the accuracy required in this
novel strcture will achieve a low-power and low-voltage implement what we explore. Furthermore,
a novel OpAmp circuit is also addressed in this thesis. By utilizing the methods
of feedforward and current-ratio, it realizes an OpAmp of high DC gain without capacitor compensation. Then, we utilize this novel OpAmp in the Dual-Path Pipelined analog-todigital
converter what we mentioned above. To make matters even more exciting, by the
particular structure of Dual-Path Pipelined analog-to-digital converter, we can design this
OpAmp under unusual specifications to attain to an attractive lower power value.
This complete circuit is designed with a 90nm CMOS technology. Power supply voltage
is 1 V, input signal amplitude is 1.4 Vpp, resolution is 11-bit, the maximum sampling
frequency is 200MHz. At Nyquist rate, the maximum power consumption is 5.3mW.
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author2 |
Wu, Jieh-Tsorng |
author_facet |
Wu, Jieh-Tsorng Chai, Angelia Yolanda 翟芸 |
author |
Chai, Angelia Yolanda 翟芸 |
spellingShingle |
Chai, Angelia Yolanda 翟芸 A Low-Power Low-Voltage Dual-Path Pipelined ADC |
author_sort |
Chai, Angelia Yolanda |
title |
A Low-Power Low-Voltage Dual-Path Pipelined ADC |
title_short |
A Low-Power Low-Voltage Dual-Path Pipelined ADC |
title_full |
A Low-Power Low-Voltage Dual-Path Pipelined ADC |
title_fullStr |
A Low-Power Low-Voltage Dual-Path Pipelined ADC |
title_full_unstemmed |
A Low-Power Low-Voltage Dual-Path Pipelined ADC |
title_sort |
low-power low-voltage dual-path pipelined adc |
publishDate |
2010 |
url |
http://ndltd.ncl.edu.tw/handle/41878529653789855808 |
work_keys_str_mv |
AT chaiangeliayolanda alowpowerlowvoltagedualpathpipelinedadc AT díyún alowpowerlowvoltagedualpathpipelinedadc AT chaiangeliayolanda dīgōnglǜdīdiànyāshuānglùguǎnxiànshìlèibǐshùwèizhuǎnhuànqì AT díyún dīgōnglǜdīdiànyāshuānglùguǎnxiànshìlèibǐshùwèizhuǎnhuànqì AT chaiangeliayolanda lowpowerlowvoltagedualpathpipelinedadc AT díyún lowpowerlowvoltagedualpathpipelinedadc |
_version_ |
1718227071067488256 |