Design and Implementation of Synchronization Detection for IEEE 802.15.3c

• Main Authors: Huang, Ya-Shiue, 黃雅雪
• Other Authors: Jou, Shyh-Jye
• Format: Others
• Language: en_US
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/38845188255711914060

碩士 === 國立交通大學 === 電子研究所 === 99 === In this thesis, a jointed preamble/boundary detection and fractional CFO estimation design is presented which supports dual SC/HSI modes of IEEE 802.15.3c applications. Based on correlation based algorithms which utilizes the structure of preamble, an efficiency architecture is proposed which realizes synchronization detection with a sequential detection scheme and a single hardware for dual SC/HSI modes and three detection operations. In order to achieve the requirement of sampling frequency, the baseband design is 8x parallelism and is operating at 333 MHz clock rate. The achieved bit error rate (uncoded) at 12 dB SNR for SC and HSI modes are 8.92×10-4 and 1.43×10-2, respectively. The proposed architecture of synchronization detection is implemented using 65 nm 1P9M CMOS process and the total gate count is 189k with power consumption of 60.16 mW including memory elements which occupies 63.26 % and can be shared with the frequency domain equalizer. Moreover, the power consumption is saved 42.5 % by applying low power techniques.