Design and Implementation of Synchronization Detection for IEEE 802.15.3c
碩士 === 國立交通大學 === 電子研究所 === 99 === In this thesis, a jointed preamble/boundary detection and fractional CFO estimation design is presented which supports dual SC/HSI modes of IEEE 802.15.3c applications. Based on correlation based algorithms which utilizes the structure of preamble, an efficiency ar...
Main Authors: | , |
---|---|
Other Authors: | |
Format: | Others |
Language: | en_US |
Published: |
2010
|
Online Access: | http://ndltd.ncl.edu.tw/handle/38845188255711914060 |
id |
ndltd-TW-099NCTU5428055 |
---|---|
record_format |
oai_dc |
spelling |
ndltd-TW-099NCTU54280552016-04-18T04:21:47Z http://ndltd.ncl.edu.tw/handle/38845188255711914060 Design and Implementation of Synchronization Detection for IEEE 802.15.3c IEEE 802.15.3c 之同步偵測的設計與實作 Huang, Ya-Shiue 黃雅雪 碩士 國立交通大學 電子研究所 99 In this thesis, a jointed preamble/boundary detection and fractional CFO estimation design is presented which supports dual SC/HSI modes of IEEE 802.15.3c applications. Based on correlation based algorithms which utilizes the structure of preamble, an efficiency architecture is proposed which realizes synchronization detection with a sequential detection scheme and a single hardware for dual SC/HSI modes and three detection operations. In order to achieve the requirement of sampling frequency, the baseband design is 8x parallelism and is operating at 333 MHz clock rate. The achieved bit error rate (uncoded) at 12 dB SNR for SC and HSI modes are 8.92×10-4 and 1.43×10-2, respectively. The proposed architecture of synchronization detection is implemented using 65 nm 1P9M CMOS process and the total gate count is 189k with power consumption of 60.16 mW including memory elements which occupies 63.26 % and can be shared with the frequency domain equalizer. Moreover, the power consumption is saved 42.5 % by applying low power techniques. Jou, Shyh-Jye 周世傑 2010 學位論文 ; thesis 61 en_US |
collection |
NDLTD |
language |
en_US |
format |
Others
|
sources |
NDLTD |
description |
碩士 === 國立交通大學 === 電子研究所 === 99 === In this thesis, a jointed preamble/boundary detection and fractional CFO estimation design is presented which supports dual SC/HSI modes of IEEE 802.15.3c applications. Based on correlation based algorithms which utilizes the structure of preamble, an efficiency architecture is proposed which realizes synchronization detection with a sequential detection scheme and a single hardware for dual SC/HSI modes and three detection operations. In order to achieve the requirement of sampling frequency, the baseband design is 8x parallelism and is operating at 333 MHz clock rate. The achieved bit error rate (uncoded) at 12 dB SNR for SC and HSI modes are 8.92×10-4 and 1.43×10-2, respectively. The proposed architecture of synchronization detection is implemented using 65 nm 1P9M CMOS process and the total gate count is 189k with power consumption of 60.16 mW including memory elements which occupies 63.26 % and can be shared with the frequency domain equalizer. Moreover, the power consumption is saved 42.5 % by applying low power techniques.
|
author2 |
Jou, Shyh-Jye |
author_facet |
Jou, Shyh-Jye Huang, Ya-Shiue 黃雅雪 |
author |
Huang, Ya-Shiue 黃雅雪 |
spellingShingle |
Huang, Ya-Shiue 黃雅雪 Design and Implementation of Synchronization Detection for IEEE 802.15.3c |
author_sort |
Huang, Ya-Shiue |
title |
Design and Implementation of Synchronization Detection for IEEE 802.15.3c |
title_short |
Design and Implementation of Synchronization Detection for IEEE 802.15.3c |
title_full |
Design and Implementation of Synchronization Detection for IEEE 802.15.3c |
title_fullStr |
Design and Implementation of Synchronization Detection for IEEE 802.15.3c |
title_full_unstemmed |
Design and Implementation of Synchronization Detection for IEEE 802.15.3c |
title_sort |
design and implementation of synchronization detection for ieee 802.15.3c |
publishDate |
2010 |
url |
http://ndltd.ncl.edu.tw/handle/38845188255711914060 |
work_keys_str_mv |
AT huangyashiue designandimplementationofsynchronizationdetectionforieee802153c AT huángyǎxuě designandimplementationofsynchronizationdetectionforieee802153c AT huangyashiue ieee802153czhītóngbùzhēncèdeshèjìyǔshízuò AT huángyǎxuě ieee802153czhītóngbùzhēncèdeshèjìyǔshízuò |
_version_ |
1718227087280570368 |