Design of CMOS Receivers for Optical Communications

• Main Authors: Chou, Shun-Tien, 周順天
• Other Authors: Chen, Wei-Zen
• Format: Others
• Language: zh-TW
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/62120236147975475325

碩士 === 國立交通大學 === 電子研究所 === 99 === With the rapid development of multimedia information, people need higher data transfer efficiency. Many applications such as HDMI cable and USB 4.0 are expected to design more than 10 Gbps operating speed. Data communication over optical links benefits from wider bandwidth and lower channel loss compared to electrical counterparts. Fiber channels are widely deployed for long haul telecommunications as network backbone. Optical links are drawing more and more attentions in these applications for their superiorities in less cross-talk, lower EMI, and fewer equalizer needed for data rate up to 10 Gbps. As a result, implementation of optoelectronic integrated circuits (OEIC) in CMOS technology with small form factor and low cost becomes a challenging and practical research topic for the SOC design of the high density communication platform. This thesis consists of two chips, respectively, 10 Gbps CMOS OEIC with adaptive equalizer in 90-nm CMOS technology and 40 Gbps optical receiver analog front-end in 65 -nm CMOS technology. The 10 Gbps CMOS OEIC consists of a novel spatially-modulated photo detector (SMPD) under a low reverse-biased voltage of 1.2 V, a low-noise trans-impedance amplifier (TIA), a post limiting amplifier, and a adaptive equalizer on a single chip. The optical receiver is capable of delivering 92 dBΩ conversion gain when driving 50 Ω output loads. The input sensitivity of the optical receiver is about 30 ?嫀pp, and the measured responsivity of the photo detector is about 37 mA/W. The input sensitivity of the optical receiver is -4 dBm for BER less than 10-12 under 27 - 1 PRBS test pattern. The core circuit dissipates 130 mW. Fabricated in 90 nm CMOS technology, chip size is 0.57mm2. The 40 Gbps optical receiver analog front-end integrating both transimpedance amplifier and limiting amplifier is presented. Incorporating nested feedback, split-node series peaking, and shunt peaking techniques, the optical receiver provides a conversion gain of 92 dBΩ, -3dB bandwidth of 35 GHz, and 800mV differential output voltage swing. The average input referred noise of the optical receiver is 14 pA/√Hz. The core circuit dissipates 168 mW. Fabricated in 65 nm CMOS technology, chip size is 0.825mm2.