| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 99 === Low-Density parity check (LDPC) code was first introduced by Dr. Gallager in 1962. This code has very much better error detection and error correction performances than other codes. It can achieve performance close to Shannon bound. In the recent years, LDPC codes have been adopted by many communication systems.
Since LDPC codes have good performance but high complexity, this thesis focuses on the complexity reduction in the hardware implementation. In this thesis, we proposed the LDPC decoder architecture for the code construction of 1/2-rate in the 802.15.3c communication standard. Considering the trade-off between performance and hardware complexity, we adopt partially-parallel CNU architecture and fully-parallel BNU architecture, and use layered decoding scheme for the decoding procedure. By using layered decoding scheme, the required iteration number is reduced and the required message memory is reduced by about 50%.
Before implementing the decoder hardware, we reorder the parity-check matrix in order to reduce the required number of CNUs, BNUs, and routing networks. We found that the combinational-logic area in the LDPC decoder is reduced by about 30% after reordering the parity-check matrix.
In the CNU architecture, we proposed a new comparison scheme and named it Iterative 2-Min Modular (IMM) comparison scheme, which can be viewed as the compromise design between the existing Double-elimination (DE) scheme and Trace-back (TB) scheme. It has the advantage of high speed and low complexity. For some specific number of CNU inputs, it takes the shortest latency and the least required comparators. By using this comparison scheme, we can further reduce the CNU area. According to the synthesis result, the IMM comparison scheme provides the smallest area than the other comparison schemes in the same time constrain. By adopting the IMM comparison scheme, the CNU area is reduced by about 26%.
At the end, we implement the non-uniform quantization scheme in the decoder architecture. As a result, compared with the general uniform quantization architectures, it has a slight performance loss which is about 0.1dB at BER 10-6, and it can reduce the overall decoder area by about 2%.
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