| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 99 === These days the clock generator integrated with other system is needed to realize high speed computation. Spurious tones and phase noise often play a critical role in measuring quality. Random jitter is significantly reduced in Multiplying Delay-Locked Loops (MDLL), phase realigning clock multipliers, compared to that in typical Phase-Locked Loops (PLL). This is performed by launching the reference edge directly into their voltage controlled oscillators (VCO) or their delayline. However, the timing mismatch in singal path to the detector as well as non-idealities of analog property in the circuits casuse a significant increase in deterministic jitter. So dealing with the spurious tone the same as deterministic jitter is this research topic. On the other hand, the channel efficiency of communication system used by the fractional-N frequency synthesizer is much higher than that used by the integer-N frequency synthesizer. The sigma delta modulator adopted in fractional- N frequency synthesizer achieves the resolution of fractional-N by generating the fractional number in average and have the property of programmable. Yet the frequency of the reference clock is not limited and not confined within the modulation signal, which gives greater design flexibility at the system level. Recently fractional- N frequency synthesizer mainly uses fractional- N frequency PLL to serve as the supply of the clock. How to reduce to phase noise contributed from jitter accumulation of the PLL/MDLL on commutation systems is the main point of our invention.
The realization of the concept of the adjustment of the reference clock on fractional- N based MDLL is that, first to know quantized information compared between the reference clock and the divided clock, generated from divider having divider ratios modulated by the sigma delta modulator (ΣΔ) to achieve fractional – N resolution. Reload the reference clock correctly or not that cause serious problems of phase offset. We modify the sigma delta modulator (ΣΔ) to predict the signal of the residue (residue[k]), which is synchronized with the error compared between the reference clock and the divided clock. The modified sigma delta modulator (ΣΔ) consists of three parts, the sigma delta modulator changing the divider ratio, the accumulator counting the reference edge, and the residual sigma delta modulator on the feedback loop. The point is this feedback loop make the the residue (residue[k]) avoiding the phase offset to align the reference edge. The residue (residue[k]) is used to determine the time of the reload of the reference clock, and let the delay line has the ability of the alignment. Because of the elimination of jitter accumulation, quantization noise of the sigma delta modulator and the noise from the reference clock induced phase noise is the bottleneck in state-of the-art synthesizer design.
Under this circumstance we propose a general form of MDLLs, which have the adjustment by reference clock, and can keep the advantage to prune away jitter accumulation. This general form composes of a multi-phase generator, a delay line, and the digital controller. The clock phases from the multi-phase generator can be reloaded in the delay line and the digital controller determines the allowance to reload the clock phase and the order of reload. If the order is random pattern, the spurs caused by the adjustment can attenuate effectively. The value of attenuation can be predicted by the theorem of Markov Chain. For example, the multi-phase generator implemented by a delay line which is rounded by delay cells use the order N+ΔN, ΔN is random variable, to inject the second delay line to reduce the spurs. The amount of the reduction of spurs and the phase increment are verified under both behavior simulation and math, and less than 6dB.
Note that the invention is not limited to ADC system, but is applicable to other systems and integrated circuits that have low noise, fractional – N resolution of MDLL.
|
|---|
