Multiplied Delay Locked Loop Based Fractional-N Frequency Synthesizer
碩士 === 國立交通大學 === 電子研究所 === 99 === These days the clock generator integrated with other system is needed to realize high speed computation. Spurious tones and phase noise often play a critical role in measuring quality. Random jitter is significantly reduced in Multiplying Delay-Locked Loops (MD...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/81114399005886347890 |