Adaptive Power Management Designs for 2D and TSV 3DIC Applications

• Main Authors: Hsieh, Wei-Chih, 謝維致
• Other Authors: Hwang, Wei
• Format: Others
• Language: zh-TW
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/05092896418903241771

博士 === 國立交通大學 === 電子研究所 === 99 === Adaptive power management designs are presented in this thesis including an all digital controlled linear regulator and an adaptive power control technique. Each one is essentially a stand-alone attachment for digital integrated circuit blocks while they can also be adopted jointly to have more flexibility on power control. Since the analog regulator design has suffered a lot from technology advancing, an all digital controlled variable output linear voltage regulator that supports voltage scaling is presented in this thesis. A test chip had been fabricated on UMC 65nm standard CMOS technology. The developed digital voltage regulator has a 99.8% current efficiency with only 164.5_A quiescent current. The area of the control system is about 300um^2. A response time constraint has been developed as well to provide a design guideline for (all) the digital control system. It describes the correlation between required speed of the digital control system, the output performance, and the size of the decoupling capacitor. A proposed time interleaving control can have trade-off between these parameters. The adaptive power control technique can utilize unused slack and reduce power. The switching state determination mechanism is the core technique replacing the critical path replica to detect circuit speed. It is intrinsically tolerant of PVT variations. The circuit speed can be altered by dynamically configuring the size of the power gating devices and hence reduce power. A test chip had been fabricated on UMC 90nm standard CMOS technology. The area and power overhead are both around 1% relative to a 32-bit multiplier. The proposed technique can achieve averages of 56.5% slack utilization, 12.39% net power reduction, and 87.5% leakage reduction. The adaptive power management designs are discussed on 2D planar and TSV 3DIC applications with temperature-aware power management methodology. A multi-layer power delivery structure is presented as well when going to TSV 3DIC applications.