Data Converters for PRML Read Channel and LCD Column Driver Applications

• Main Authors: Li, Ren-Wei, 李人維
• Other Authors: Hung, Chung-Chih
• Format: Others
• Language: zh-TW
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/31004312734692574477

碩士 === 國立交通大學 === 電信工程研究所 === 99 === Performance and power consumption of analog-to-digital converters (ADCs) affect the efficiency of an entire system. In this thesis, we focus on the development of the design techniques for high speed ADCs, and propose a 6-bit high speed ADC design using resistive averaging techniques. The ADC includes an on-chip Track/Hold circuit to eliminate the sampling time skews resulted from the fact that the clock and input signal are transmitted to numerous comparators, and further enhance the dynamic performance. In addition, there are elaborated considerations made for enabling digital encoders to be operated stably at high speed. LCD column drivers have traditionally used the nonlinear R-string style digital-to-analog converter (DAC). This thesis describes a switch capacitor digital-to-analog converter, which transfers one bit within 5us and consumes less than 2uA. Compared with the traditional digital-to-analog converter, there is a substantial reduction on areas. And when the resolution increases, the area does not grow exponentially.