A Study on the Facility Layout for a Multi-Cell and Multi-Bay Manufacturing System

• Main Authors: Ta-Wei Liao, 廖大偉
• Other Authors: Ying-Chin Ho
• Format: Others
• Language: en_US
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/51769481500045004513

博士 === 國立中央大學 === 工業管理研究所 === 99 === Multi-cell (Cellular) manufacturing system (CMS) and multi-bay manufacturing system have become very important research topics in the facility layout problems. CMS is an innovative manufacturing strategy that combines the advantages of a job shop’s flexibility and a flow shop’s efficiency. In the first part of this paper, we study the Input/Output point location problem and the intra-cell flow path layout problem of cells in a cellular manufacturing system. Traditional approaches have often solved these two problems as separate problems, despite they are mutually affected. As a result, the results obtained by traditional approaches may not be as desirable as expected. In this study, we propose a layout procedure that can solve these two problems concurrently, so that the sum of the inter-cell flow distance and the intra-cell flow distance can be minimized. We assume cells have been arranged along a straight-line inter-cell flow path, and the configuration of intra-cell flow paths is serpentine. The proposed layout procedure classifies the flow distance incurred by inter-cell flow into five types and minimizes them with different solution procedures containing various linear programming models. We use an example to illustrate the proposed layout procedure. The results of the example show that the proposed layout procedure can effectively find each cell’s I/O point locations and intra-cell flow path layout by considering both intra-cell and inter-cell flow distance at the same time. In this paper, we also study the multi-bay layout problem in a semiconductor fab. One unique characteristic of this bay layout problem is that bays are connected by two inter-bay guide path loops – a spine guide-path loop and a perimeter guide-path loop. To ensure bays can be correctly arranged on the floor and connected by both guide path loops, this dual-loop guide path configuration must be considered throughout the entire layout design procedure. To achieve this goal, we propose a layout design method that considers not only the layout of bays, but also the layout of guide path loops. Furthermore, to ensure the feasibility and quality of the layout results, the proposed layout method solves these two layout problems simultaneously. Since semiconductor fabs often have shortcuts set up on their spine guide path loops, the problem of setting up shortcuts is also studied here. The objective of the proposed layout method is to minimize the total inter-bay flow distance of wafer cassettes. Heuristic methods and mathematical programming models are developed to assist us in achieving this objective. We solve an example problem to illustrate the proposed layout method. The example problem also demonstrates the capability of the proposed layout method in producing feasible and good-quality bay layouts with both spine and perimeter guide path loops.