Summary: | 碩士 === 國立中央大學 === 資訊工程研究所 === 99 === A typical Solid-State Disk controller usually uses a processor as the core of flash memory management that can execute Flash Translation Layer middleware. The purpose of FTL algorithm is to manage flash memory effectively. Generally, these algorithms which have high computational complexity cause the processor difficult to load. Some use the high performance processor to put up with the complexity of algorithms, which will lead to increasing power consumption and cost. The Solid-State Disk controller that this paper proposes is design FTL algorithm to be a core of high performance hardware to achieve a high speed hardware-based Solid-State Disk controller. With this method, it can decrease the time in running the algorithm to improve the performance of the controller while reducing power consumption.
We use hierarchical and modular system design method to design the hardware of the complex algorithm, and meanwhile we use GRAFCET modeling to describe the behavior of discrete event of each module. Finally we synthesize the design to VHDL-based hardware intelligent property and verify it on FPGA platform, integrating this hardware-based Solid-State Disk controller into the existing Solid-State system architecture. The experiments show that compared with the controller that uses 8-bit processor to run FTL algorithm, our system can reduce 33% of the access time and 29% of power consumption.
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