| Summary: | 博士 === 國立中央大學 === 電機工程研究所 === 99 === As semiconductor technology continues to shrink, the process variation problems will become inevitable. It is anticipated that the problem of uncontrollable process variation will become more serious. As a result, yield loss caused by process variation is becoming an
important design issue. The key performance of many analog circuits is directly related to accurate capacitor ratios. In general, capacitor mismatches caused by process variation can be classified as two types: random mismatch and systematic mismatch. To analyze process variation in early design stages, process variation information must be input to a circuit simulator, where Monte-Carlo analysis is commonly employed to find out process variation
information and to eliminate the random mismatch in the early stages of design. On the other hand, systematic mismatch is mainly due to asymmetrical layout and processing gradients. The common centroid approach is commonly employed to reduce device mismatches caused
by symmetrical layouts and processing gradients. Among the candidate placements generated by the common centroid approach, however, whichever achieves better matching is generally difficult to be determined without performing the time-consuming yield evaluation process.
This study addresses the impact of capacitor correlation on the yield enhancement of switched-capacitor integrated circuits. The relationships between correlation and mismatch and between correlation and variation of capacitor ratio are also presented. Therefore, both
mismatch and variation of capacitor ratio can be expressed in term of capacitor correlation. Based on a spatial correlation model, this study proposes a design methodology for yield enhancement of analog circuits using switched-capacitor techniques. An efficient and
effective placement generator is developed to derive a placement for a circuit to achieve the highest or near highest correlation coefficient and thus accomplishing a better yield performance. A simple yield analysis is also developed to evaluate the achieved yieldperformance of a derived placement. Results show that the proposed methodology derives a placement which achieves better yield performance than those generated by the common
centroid approach. Furthermore, both process variation and device mismatch are considered in the early design phase to reduce the design costs and speed-up the time to market.
|
|---|
