Design Methodology for Yield Enhancement of Switched-Capacitor Analog Integrated Circuits
博士 === 國立中央大學 === 電機工程研究所 === 99 === As semiconductor technology continues to shrink, the process variation problems will become inevitable. It is anticipated that the problem of uncontrollable process variation will become more serious. As a result, yield loss caused by process variation is becomin...
Main Authors: | Pei-Wen Luo, 羅珮文 |
---|---|
Other Authors: | Chin-Long Wey |
Format: | Others |
Language: | en_US |
Published: |
2011
|
Online Access: | http://ndltd.ncl.edu.tw/handle/43125368937385532243 |
Similar Items
-
Design Methodology for Yield Enhancement of Switched-Capacitor Analog Integrated Circuits
by: Pei-Wen Luo, et al.
Published: (2011) -
Design of nonlinear analog switched capacitor circuits
by: Liu, Jie-Cheng, et al.
Published: (1986) -
Variation-Aware Placement of Common-Centroid Unit Capacitor Array for Switched-Capacitor Analog Circuits
by: Chien-Chih Huang, et al.
Published: (2016) -
Microwatt Switched Capacitor Circuit Design
by: E. Vittoz
Published: (1982-01-01) -
Studies on switched-capacitor circuit design
by: CAI, ZHANG-REN, et al.
Published: (1986)