Native-Conflict-Aware Track Routing for Double Patterning Technology
碩士 === 國立中央大學 === 電機工程研究所 === 99 === As the manufacturing process advances, the size of integrated circuits has shrunk into the 32 nm. Lithography process encounters a bottleneck due to printability and manufacturability issues. Recently, double patterning lithography（DPL）has been proposed for the m...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/61129363643392170814 |