Design and Implementation of Turbo Decoder for 3GPP-LTE Advanced Systems
碩士 === 國立中央大學 === 電機工程研究所 === 99 === In this thesis, we design the Turbo decoder applies to channel coding system for the 3rd Generation Partnership Project (3GPP) specification. The decoder implements the MLMAP algorithm with high radix and high parallel architecture. In timing chart of decoding, w...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/81853333628801338554 |
| Summary: | 碩士 === 國立中央大學 === 電機工程研究所 === 99 === In this thesis, we design the Turbo decoder applies to channel coding system for the 3rd Generation Partnership Project (3GPP) specification. The decoder implements the MLMAP algorithm with high radix and high parallel architecture. In timing chart of decoding, we utilize the sliding-window and warm-up scheme to improve the decoding period and performance. We utilize the NII scheme to compensate the performance loss caused by the high parallel architecture design. We propose the simpler and faster switch network than previous literatures. The memory area is reduced by reducing the number of memory blocks. The CSO unit is an important component of MLMAP implementation and we choose one structure as our best tradeoff from few different CSO structures. The proposed Turbo decoder can achieve operation frequency 425 MHz and throughput 950Mb/s per MLMAP decoder.
|
|---|