| Summary: | 碩士 === 國立彰化師範大學 === 電子工程學系 === 99 === Content addressable memory, a high-performance lookup engine in many systems, is widely used in communication network and cache system. However, owing to the mass and parallel comparison, the area overhead, power dissipation and reliability are still the major issues for a content addressable memory device.
In this thesis the Berger code, a well-known error-detection code, is applied in the binary-valued content-addressable memory design to reduce the redundant area of the logic transistor stacks. A three-transistor DRAM based binary-valued content-addressable memory cell is then innovated. Furthermore an improved coding technique called Berger Invert code is developed to promote the dependability especially when the DRAM is approximated to a fully-asymmetric system. The coding cannot only approve to reduce the redundant transistors but also provide a totally self-check for refresh and error detection mechanism for reliability.
Eventually this paper presents a DRAM-based CAM based on Berger invert code with dependable and area efficient. Especially for memory with seriously asymmetrically retention error probability, the novel Berger invert code is presented for improve the dependability for about 21% and information energy for 25%.
In addition, the SRAM-based CAM based on Berger invert code design was implemented with the TSMC 0.18 CMOS technology under 1.8 V supply voltage. The Search-to-Match delay time of a 64 words by 14 bits BIC-CAM is about 1.62ns.
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